S5L33M安霸Ambarella ARM四核cpu宽动态H.264,H.265编码器ISP SoC 4K30FPS网络安防监控摄像机主控芯片Security Camera DSP
概要描述
S5L33M是一款集成的系统级芯片(SoC)平台，针对家庭IP摄像头，具有高达2Mp30 + 480p30的视频性能。
S5L33M芯片为定制应用提供了四核600 MHz Arm Cortex -A53 CPU，高性能数字信号处理(DSP)子系统，图像传感器管道(ISP)，高性能的H.265 / HEVC和H.264 / AVC编码器，能够同时进行视频录制和流媒体。
关键特性
• 嵌入式Arm四核Cortex-A53 600 MHz CPU, L2缓存
• 智能视频压缩优化监控场景，2Mp30低至512kbits /s
• 双独立传感器输入
• 高达320万像素/s的输入像素率
• 广角镜头的镜头失真校正
• 高级动态范围(WDR和HDR)引擎
• 3D运动补偿降噪(MCTF)
• H.264 / H.265编码性能高达2Mp30 +二级流
• H.265和H.264编码流的同时流
• 256-pin, 0.65 mm间距FC TFBGA封装(11mmx11mm)
• 14纳米CMOS低功耗(LP)技术
• 工作温度从-20℃到+85℃
1. 概述
这是Ambarella的S5L33M处理器的初步数据表，首先简要介绍了该芯片(章节1.1)和关键特性(章节1.2)的总结。第2章描述了S5L33M的外设接口。关于引脚细节和电气特性，请分别参阅第3章和第4章。请参阅规格书第5章包装信息和规格书第6章Ambarella联系和订购细节。
请注意，本数据表中描述的芯片特性可能会更改。尚未完全确定的细节(例如，编码细节)使用保守估计提供(例如，最终编码性能预期达到或超过提供的估计)。请联系Ambarella代表获取更多信息。
1.1介绍
S5L33M是一个集成的SoC平台，针对2M - 5M视频和HDR支持的低功耗IP摄像头，包括服务提供商应用程序和居民级应用程序的云存储服务。S5L33M芯片是一款四核Cortex-A53 Arm处理器，具有数字信号处理(DSP)子系统和图像信号处理器(ISP)，以及高性能的H.265 / HEVC和H.264 / AVC编码引擎，可同时进行流媒体处理。下面给出了S5L33M SoC的功能框图。
S5L33M SoC提供了串行sub-LVDS、SLVS、HiSPi和MIPI接口的无胶接口，以及与流行CMOS图像传感器的并行连接。ISP提供先进的图像处理功能，包括改进的多曝光高动态范围(HDR)处理，宽动态范围(WDR)单曝光色调映射与局部对比度增强，3D运动补偿噪声降低(MCTF)，边缘增强，鱼眼镜头失真校正与直线和全景模式高达180度。
H.264 / H.265编解码器引擎提供的通用编码高达2Mp30 + 480p30 + 2Mp1 / 2Mp30 + 480p30 + 2Mp1的总性能，包括同步编码流。该编码器实现了全功能的H.265/HEVC和H.264/AVC视频编码，实现了最高质量和最低的比特率。这些函数包括双向预测(b帧)、大运动估计搜索范围和宏块级量化。Ambarella建立了灵活的多流功能，允许实时运行
启动/停止以及调整比特率，帧速率，和每个单独的流的GOP。
600mhz四核Arm Cortex-A53 CPU, NEON DSP扩展和浮点支持，实现全功能的用户应用。
S5LM系列采用低功耗14纳米CMOS技术制作，并集成了先进的节能模式，如利用dsp子系统的存储资源，以减少外部存储带宽和相机系统总功耗需求。
概述
安霸S5L IP相机SoC集成先进图像传感器管道(ISP)， H.265和H.264编码器能够达到4Kp30视频，和一个四核ARM®Cortex™-53 CPU高达1 GHz实现自定义应用程序。低功率的S5L适用于广泛的专业IP相机设计，提供先进图像特征，如HDR处理，运动补偿3D降噪，双VIN，镜头畸变校正。灵活的S5L SDK提供了一个基于linux的框架
开发环境，包括映像调优工具和一组丰富的APIs，支持一系列产品定制和在传感器和镜头调整等领域的差异化选择，分析和网络应用。
关键特性
灵活的低功耗平台：
※ 64位ARM®四核皮质™-A53 CPU到1.0 GHz, L2缓存；
※ Linux内核版本4.9+(64位)；
※ 用于基于标准开发的Linux SDK；
※ 14nm低功耗CMOS工艺；
先进的图像处理：
※ 高达大于4.8亿像素/秒的输入速率
※ 多曝光线交织HDR
※ 硬件镜头畸变校正
※ 电子图像稳定(EIS)
※ 3D运动补偿降噪(MCTF)
高效视频编码
※ H.265和H.264视频压缩
※ 灵活多流
※ 高达4Kp30 + 480p30的视频性能为H.265
※ 智能的H.264和H.265编码器算法
SUMMARY DESCRIPTION
The S5L33M is an integrated system-on-a-chip (SoC) platform that targets home IP cameras with up to 2Mp30 + 480p30 video performance.
S5L33M chips provide a quad-core 600 MHz Arm® Cortex®-A53 CPU for custom applications, a highperformance digital signal processing (DSP) subsystem with an image sensor pipeline (ISP), and high-performance H.265 / HEVC and H.264 / AVC encoders capable of simultaneous video recording and streaming.
KEY FEATURES
• Embedded Arm quad-core Cortex-A53 600 MHz CPU with L2 cache
• Smart video compression optimized for surveillance scenes, 2Mp30 as low as 512 Kbits/s
• Dual independent sensor inputs
• Up to 320 MPixel/s input pixel rate
• Lens distortion correction for wide-angle lenses
• Advanced dynamic range (WDR and HDR) engine
• 3D motion-compensated noise reduction (MCTF)
• H.264 / H.265 encode performance up to 2Mp30 plus secondary streams
• Simultaneous streaming of H.265 and H.264 encoded streams
• 256-pin, 0.65-mm pitch FC TFBGA package (11mmx11mm)
• 14 nm CMOS low power (LP) technology
• Operating temperature from -20 C to +85 C
1. OVERVIEW
This preliminary datasheet for the S5L33M processor from Ambarella begins with a brief introduction to the chip (Section 1.1) and a summary of key features (Section 1.2). Chapter 2 describes the S5L33M peripheral interfaces. For pin details and electrical characteristics refer to Chapter 3 and Chapter 4, respectively. See Chapter 5 for package information and Chapter 6 for Ambarella contact and ordering details.
Please note that the chip features described in this datasheet are subject to change. Details that have not been entirely finalized (e.g., encoding specifics) are provided using conservative estimates (i.e., final encoding performance is expected to meet or exceed the estimate provided). Please contact an Ambarella representative for additional information.
1.1 Introduction
The S5L33M is an integrated SoC platform that targets low-power IP cameras with 2M - 5M video and HDR support, including service provider applications and cloud storage services for residential-level applications. S5L33M chip provides a quad-core Cortex-A53 Arm CPU for custom applications, a digital signal processing (DSP) subsystem with an image signal processor (ISP), and a high-performance H.265 / HEVC and H.264 / AVC encoding engine capable of simultaneous streaming. A functional block diagram of the S5L33M SoC is provided below.
The S5L33M SoC provides a glueless interface to serial sub-LVDS, SLVS, HiSPi, and MIPI interfaces, as well as parallel connections to popular CMOS image sensors. The ISP offers advanced image-processing features including improved multi-exposure high dynamic range (HDR) processing, wide dynamic range (WDR) singleexposure tone mapping with local contrast enhancement, 3D motion-compensated noise reduction (MCTF), edge enhancement, and fisheye lens distortion correction with rectilinear and panorama modes for up to 180 degrees .
The H.264/H.265 codec engine delivers versatile encoding up to 2Mp30 + 480p30 + 2Mp1 / 2Mp30 + 480p30 + 2Mp1 total performance, including simultaneous encode streams. The high-efficiency encoder implements full-function H.265/HEVC and H.264/AVC video encoding for the highest-quality and lowest possible bitrate. These functions include bidirectional prediction (B-frames), large motion-estimation search range, and macroblock-level quantization. Ambarella builds in flexibility with a multi-streaming function, allowing on-the-fly
start/stop as well as the adjustment of the bitrate, frame rate, and GOP of each individual stream.
A 600 MHz quad-core Arm Cortex-A53 CPU with NEON DSP extensions and floating point support is available for implementing full-featured user applications.
The S5LM family is fabricated using low-power 14-nm CMOS technology and integrates advanced power-saving modes, such as utilizing DSP-subsystem memory resources to reduce external memory bandwidth and total camera system power requirements.
Key Features
Overview
The Ambarella S5L IP Camera SoC integrates an advanced imagesensor pipeline (ISP), H.265 and H.264 encoders capable of up to4Kp30 video, and a Quad Core ARM® Cortex™-53 CPU up to 1 GHz forimplementing custom applications. The low-power S5L is suitable fora wide range of professional IP camera designs, offering advancedimaging features such as HDR processing, motion-compensated 3Dnoise reduction, dual VIN, and lens distortion correction. The flexible S5L SDK provides a Linux-based framework anddevelopment environment that includes image-tuning tools anda rich set of APIs, enabling a range of product customization anddifferentiation options in areas such as sensor and lens tuning,analytics and network applications.
Flexible Low-Power Platform
※ 64-bit ARM Quad Core Cortex™-A53 CPU up to1.0 GHz with L2 cache
※ Linux kernel version 4.9+ (64-bit)
※ Linux SDK for standards-based development
※ 14-nm low-power CMOS process
Advanced Image Processing
※ More than 480 Mpixels/s input rate
※ Multi-exposure line-interleaved HDR
※ Hardware lens distortion correction
※ Electronic Image Stabilization (EIS)
※ Dual Independent sensor inputs
※ 3D motion compensated noise reduction (MCTF)
High-Efficiency Video Encoding
※ H.265 and H.264 video compression
※ Flexible multi-streaming
※ Up to 4Kp30 + 480p30 video performance for H.265
※ Smart H.264 and H.265 encoder algorithms
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